Computer Engineering @ UBC · Expected May 2027
Ahmad Khan
I design RTL for Cyclone V FPGAs, write the testbenches that find its bugs, and publish the numbers either way.
Projects
four, each measured
test image 0 · ten Q8.8 logits · argmax 7
Fixed-Point Neural Network Accelerator
SystemVerilog · UVM · Questa · Nios II
- MNIST accuracy, Q8.8
- 95.27%
- per inference at 50 MHz
- 1.56 ms
- Fmax, +6.3 ns slack
- 73 MHz
2²² keys · one core, or two from both ends
Dual-Core RC4 Key-Search Engine
SystemVerilog · Questa · SignalTap
- cycles per candidate key
- 4,299
- min, worst-case search, 1 → 2 cores
- 6.0→3.0
- Fmax, 1,162 ALMs
- 79 MHz
27 MHz · 50 MHz · one clean cycle
Real-Time FPGA Audio Player
Verilog · Avalon-MM · CDC
- 8-bit samples from flash
- 2 MiB
- MHz, clock-domain crossing closed
- 27→50
- Fmax on CLOCK_50
- 76 MHz
10 / 10 / 12 split · R/W/X · random TLB eviction
OS/161 Kernel
C · MIPS · sys161 · GDB
- process syscalls, solo
- 6
- page table replacing DUMBVM
- 2-level
- file syscalls, with a lab partner
- 8
Skills
- Design
- RTL design, microarchitecture, datapath and control, FSM design, clock-domain crossing, fixed-point (Q-format) arithmetic, synthesis, static timing analysis, timing closure
- Verification
- UVM 1.2 (driver, monitor, sequencer, reactive responder, scoreboard), golden-model checking, randomized stimulus with back-pressure and latency injection, FSM state/transition coverage, SignalTap
- Tools
- Quartus Prime, Questa, ModelSim, Platform Designer, Nios II SBT, Git, Linux, GDB, Avalon-MM slave and master, on-chip M10K RAM, EPCQ serial flash, JTAG UART, PS/2, I2C
Contact
- email ahmadkasad1357@gmail.com
- github github.com/1ahmadkhan1
- linkedin linkedin.com/in/1ahmadkhan1