Fixed-Point Neural Network Accelerator

Everything is on-chip M10K RAM; nothing goes to SDRAM. The whole system, CPU included, fits in 2,152 ALMs (7% of the chip), 108 M10K blocks (27%) and 756,224 memory bits (19%). The accelerator's control registers sit at 0x10100 on the fabric.

The bias memories double as output buffers: layer 1 reads B1 as its bias vector and writes the 16 activations back into B1, so layer 2 uses B1 as its input. That saves memory blocks but makes a second inference need the biases reloaded, which is one of the things the section on write-back comes back to.

Ten test images were exported as .mif for on-board runs. The 95.27% figure is from the bit-accurate Python model of the same Q8.8 arithmetic run over all 10,000 test images (testing/test_accuracy.py), not from streaming 10,000 images through the board.

The slave never stalls: s1_waitrequest is tied low and writes land in one cycle. done is simply bit 4 of the state encoding, set only in done_out_st and wait_start_st, so the readback costs no extra logic. The driver sequence per layer is: write registers 1 to 6, write start = 1, poll register 0 until done, write start = 0.

The registers are read live by the FSM, not latched at start. A later test (acc_latch_test) showed that a CSR write during a job changes the job mid-flight. See the last section for what that implies.

The read_* states each have a self-loop for the cycles spent waiting on the bus, and write_wait_st has one for a stalled write. Those five self-loops plus idle and wait_start waiting are what make the transition count 21 rather than 14.

Addresses: bias at bias_base + 2i, input at input_base + 2j, weight at weights_base + 2(i × input_size + j). The i × input_size multiply is one of the four DSP blocks.

The read handshake is: raise read with the address; keep it raised while waitrequest is high; drop it the cycle after the request is accepted; then sit in the same state until readdatavalid arrives. The design keeps exactly one outstanding read in flight, so every cycle of memory latency is paid twice per MAC, once for x and once for w.

That is where the cycle count comes from. With ideal 1-cycle memory the loop is inner_loop (1) + read_2 (2) + read_3 (2) + dot (1) = 6 cycles per MAC: 12,960 MACs in 78,102 cycles, 6.03 cycles per MAC measured. With 4-cycle latency the same bench measures 155,988 cycles, 12.04 per MAC. The critical path in the timing report runs from the fabric's response FIFO into the weight register, 13.05 ns.

The exact line that keeps read alive during waitrequest is the subject of the duplicate-read exhibit below.

// read_1_st: seed with the bias in Q16.16
accumulation <= $signed({{48{bias[15]}}, bias}) <<< 8;

// dot_st
accumulation <= accumulation + (x * w);   // x, w: sign-extended 16-bit in 32-bit regs
input_j      <= input_j + 1;

x and w are held in 32-bit signed registers, so the fitter builds a 32×32 signed multiply; together with the address multiply that is the 4 DSP blocks. A 16×16 multiply would be enough and is one of the things the concurrent rewrite changes.

The 64-bit accumulator cannot overflow for this network, but a later test (acc_overflow_test) found that the rounding stage shifts the 64-bit value into a 32-bit temporary before saturating. Once 512 or more products of −128.0 × −128.0 pile up, that temporary wraps and saturation picks the wrong rail. Adversarial for a trained network, but layer 1 is 784 wide, so it is inside the failing range on paper.

// done_inn_st
if (accumulation >= 0)
    output_temp <= (accumulation + 128) >>> 8;
else if (relu_enable)
    output_temp <= 0;
else
    output_temp <= -((-accumulation + 128) >>> 8);

// saturate_st
if      (output_temp >  32767) neuron_activation <=  16'sd32767;
else if (output_temp < -32768) neuron_activation <= -16'sd32768;
else                           neuron_activation <= output_temp;

The scoreboard's golden model implements the same three steps in plain integer arithmetic and compares every written activation. Across the tests it counted ReLU clamps and saturations separately so that a test which never saturates cannot claim to have checked saturation.

// write_st
if (acc_master_address[1] == 1'b0) begin
    acc_master_writedata  <= {16'b0, neuron_activation};
    acc_master_byteenable <= 4'b0011;
end else begin
    acc_master_writedata  <= {neuron_activation, 16'b0};
    acc_master_byteenable <= 4'b1100;
end
acc_master_write <= 1'b1;

// write_wait_st
if (!acc_master_waitrequest) begin
    acc_master_write <= 1'b0;
    neuron_i <= neuron_i + 1;
    input_j  <= 0;
    state    <= outer_loop_st;
end

Writing over the bias is why the system is single-shot: run the same layer twice on the same memory and the second run uses the first run's activations as biases (acc_rerun_test exists to prove exactly that). The write_wait_st self-loop is also the one transition the non-stalling tests can never reach, which is the 20/21 in the coverage exhibit.